收藏本站
CY2SSTV857
.......................... Document #: 38-07557 Rev. *E Page 3 of 8
Zero Delay Buffer
When used as a zero delay buffer the CY2SSTV857-32 will
likely be in a nested clock tree application. For these applica-
tions, the CY2SSTV857-32 offers a differential clock input pair
as a PLL reference. The CY2SSTV857-32 then can lock onto
the reference and translate with near zero delay to low-skew
outputs. For normal operation, the external feedback input,
FBIN, is connected to the feedback output, FBOUT. By
connecting the feedback output to the feedback input the
propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge
thus producing a near zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs.
When VDDA is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Power Management
Output enable/disable control of the CY2SSTV857-32 allows
the user to implement power management schemes into the
design. Outputs are three-stated/disabled when PD# is
asserted LOW (see Table 1).
Table 1. Function Table
Inputs
Outputs
PLL
AVDD
PD#
CLK
CLK#
Y
Y#
FBOUT
FBOUT#
GND
H
L
H
L
H
L
H
BYPASSED/OFF
GND
H
L
H
L
H
L
BYPASSED/OFF
XL
L
H
Z
ZZ
Off
XL
H
L
Z
ZZ
OFF
2.6V
H
L
H
L
H
L
H
On
2.6V
H
L
H
L
H
L
On
2.6V
H
< 20 MHz
Hi-Z
HI-Z
Off
CLKIN
t
(phase error)
FBIN
FBOUT
t
sk(o)
Yx
t
sk(o)
Figure 1. Phase Error and Skew Waveforms
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
CY505YC64DT IC CLK CK505 BROADWATER 64TSSOP
CYW150OXC IC CLOCK 440BX AGP 56SSOP
CYW173SXC IC CLK GEN TAPE DRV 4CH 16SOIC
CYW305OXC IC CLOCK W305 SOLANO 56SSOP
DAC5674IPHPG4 IC DAC 14BIT 400MSPS 48-HTQFP
DAC7621EBG4 IC SNGL 12BIT PARALLEL D/A 20SSO
DAC7801KPG4 IC DUAL 12BIT CMOS DAC 24-DIP
DAC8043AESZ IC DAC 12BIT MULT SRL INP 8SOIC
相关代理商/技术参数
CY2SSTV857ZXI-32T 功能描述:时钟缓冲器 2.5V 60-200MHz 1:10 Diff DDR266/333 B/D RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel
CY2V012FLXCT 制造商:Cypress Semiconductor 功能描述:
CY2V013FLXCT 功能描述:锁相环 - PLL IC XTAL OSC VOLT RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray
CY2V013FLXIT 功能描述:锁相环 - PLL FleXo HiPerf ClkGen RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray
CY2V014FLXCT 功能描述:锁相环 - PLL IC XTAL OSC VOLT RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray
CY2V014FLXIT 功能描述:锁相环 - PLL FleXo HiPerf ClkGen RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray
CY2V995 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:S2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer
CY2V9950 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer